Multi-core Technologies and Designing for Concurrency
Acquire the skills necessary to design, develop, and tune applications and systems using multi-core processors.
The Multi-core Technologies and Designing for Concurrency course provides engineers with a fast, cost-effective way to acquire the skills necessary to design, develop, and tune applications and systems using multi-core processors. Wind River® VxWorks® symmetric multiprocessing (SMP) technology is used for lab purposes, although the principles taught in this course also apply to Linux design.
After this course, participants will be able to perform the following:
- Describe multi-core processor architectures
- Identify the benefits and choices involved in leveraging multi-core processors in a new system design
- Explain the need for a new programming model
- Design and implement parallel and lock-free algorithms
- Wind River VxWorks 6.9
- Wind River Workbench 3.3
- Wind River Simics 4.6
Who Should Attend
- Engineers starting a new real-time design on a multicore system
- System architects and designers who want to extend their multicore skills
- Software developers who work on multi-core platforms
- Senior engineers who will evaluate multi-core technology
- This two-day expert-led course consists of nine lectures and seven lab sessions.
- Attendees use VxWorks 7, Workbench 4, and Simics 4.8 to gain experience with the topics presented.
- Participants receive individual guidance from an expert engineer who has extensive experience with Wind River technologies.
Introduction to Multi-core
- Why do we need multi-core?; multi-core use cases
- Who is driving the multi-core market
- Multi-core vendors and architectures
- Homogeneous and heterogeneous multi-core
- On-chip inter-connect architecture
- Uniform and non-uniform memory access
- Cache and cache coherence
- Multi-core processor benchmarks
- LAB: Getting started
- Asymmetric multiprocessing (AMP)
- Bare metal
- Multi-core inter-process communication (MIPC)
- Choosing your multi-core configuration
- LAB: Hypervisor Hello World 2 cores
The Sequential Model
- Von Neumann computer architecture
- Instruction-level parallelism
- Atomic operations
- Memory barriers
- What is parallelism?
- Why do we need parallelism?
- Types of parallelism
- Creating parallelism
Parallel Programming Model
- Parallel programming challenges
- Limits of parallel execution
- Shared memory model
- LAB: Implicit synchronization
- Concurrency and multi-threading
- Thread pools
- Threading development cycle
- Quantifying parallelism
- Problems decomposition
- Designing parallel algorithms
- Lock-free and wait-free algorithms
- LAB: Problem decomposition
- LAB: Lock granularity
- LAB: Lock-free stack
Migrating to Multi-core
- Migration challenges
- LAB: Data synchronization
- LAB: Core affinity and reservation
- C programming
- Functional knowledge of UNIX
- Basic VxWorks API knowledge
- Real-time programming basics
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